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tps92691 , tps92691-q1 slvsd68 ? december 2015 tps92691/-q1 multi-topology led driver with rail-to-rail current sense amplifier 1 features 3 description the tps92691/-q1 is a versatile led controller that 1 ? wide input voltage: 4.5 v to 65 v can support a range of step-up or step-down driver ? wide output voltage range: 2 v to 65 v topologies. the device implements a fixed-frequency ? low input offset rail-to-rail current sense peak current mode control technique with amplifier programmable switching frequency, slope compensation, and soft-start timing. it incorporates a ? better than 3% led current accuracy over high voltage (65-v) rail-to-rail current sense amplifier 25 c to 140 c junction temperature range that can directly measure led current using either a ? compatible with high-side and low-side high-side or a low-side series sense resistor. the current sense implementations amplifier is designed to achieve low input offset voltage and attain better than 3% led current ? high-impedance analog led current adjust input accuracy over junction temperature range of 25 c to (iadj) with over 15:1 contrast ratio 140 c and output common-mode voltage range of 0 ? over 1000:1 series fet pwm dimming ratio to 60 v. with integrated series n-channel dim driver led current can be independently modulated using interface either analog or pwm dimming techniques. linear ? continuous led current monitor output for analog dimming response with 15:1 range is obtained system fault detection and diagnoses by varying the voltage from 140 mv to 2.25 v across ? programmable switching frequency with external the high impedance analog adjust (iadj) input. pwm clock synchronization capability dimming of led current is achieved by modulating the pwm input pin with the desired duty cycle and ? programmable soft-start and slope frequency. optional ddrv gate driver output can be compensation used to enable series fet dimming functionality to ? comprehensive fault protection circuitry get over 1000:1 contrast ratio. including vcc undervoltage lockout (uvlo), the tps92691/-q1 supports continuous led status output overvoltage protection (ovp), cycle-by- check through the current monitor (imon) output. cycle switch current limit, and thermal this allows for led short circuit or open circuit protection detection and protection. additional fault protection ? tps92691-q1: automotive q100 grade 1 features include vcc uvlo, output ovp, switch qualified cycle-by-cycle current limit, and thermal protection. 2 applications device information (1) part number package body size (nom) ? tps92691-q1: automotive exterior lighting tps92691-q1 applications htssop (16) 5.10 mm 6.60 mm tps92691 ? architectural and general lighting applications (1) for all available packages, see the orderable addendum at the end of the data sheet. typical boost led driver application schematic efficiency vs output voltage 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. v in (v) efficiency (%) 8 9 10 11 12 13 14 15 16 17 18 75 80 85 90 95 100 d019 v o = 60 v, i led = 300 ma tps92691-q1 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vin led+ led ? vin ss rt/sync pwm comp iadj imon agnd pad vcc gate is pgnd ovp ddrv csp csn l r ov1 r ov2 r is r cs q 2 q 1 d c ss c comp r t c imon c out c vcc c in c ov r adj2 r adj1 v pwm productfolder sample &buy technical documents tools & software support &community
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com table of contents 7.4 device functional modes ........................................ 16 1 features .................................................................. 1 8 application and implementation ........................ 17 2 applications ........................................................... 1 8.1 application information ............................................ 17 3 description ............................................................. 1 8.2 typical applications ................................................ 26 4 revision history ..................................................... 2 9 power supply recommendations ...................... 37 5 pin configuration and functions ......................... 3 10 layout ................................................................... 37 6 specifications ......................................................... 4 10.1 layout guidelines ................................................. 37 6.1 absolute maximum ratings ...................................... 4 10.2 layout example .................................................... 38 6.2 esd ratings .............................................................. 4 11 device and documentation support ................. 39 6.3 recommended operating conditions ....................... 4 11.1 related links ........................................................ 39 6.4 thermal information .................................................. 5 11.2 community resources .......................................... 39 6.5 electrical characteristics ........................................... 5 11.3 trademarks ........................................................... 39 6.6 typical characteristics .............................................. 7 11.4 electrostatic discharge caution ............................ 39 7 detailed description ............................................ 11 11.5 glossary ................................................................ 39 7.1 overview ................................................................. 11 12 mechanical, packaging, and orderable 7.2 functional block diagram ....................................... 11 information ........................................................... 39 7.3 feature description ................................................. 12 4 revision history date revision notes december 2015 * initial release. 2 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 5 pin configuration and functions pwp package 16-pin htssop with powerpad ? top view pin functions pin i/o description no. name input supply for the internal vcc regulator. bypass with 100-nf capacitor to gnd located close to the 1 vin ? controller. soft-start programming pin. connect a capacitor to agnd to extend the start-up time. switching can 2 ss i/o be disabled by shorting the pin to gnd. oscillator frequency programming pin. connect a resistor to agnd to set the switching frequency. the 3 rt/sync i/o internal oscillator can be synchronized by coupling an external clock pulse through 100-nf series capacitor. pwm dimming input. driving the pin below 2.3 v (typ), turns off switching, idles the oscillator, disconnects the comp pin, and sets ddrv output to ground. the input signal duty cycle controls the 4 pwm i average led current through pwm dimming operation. connect to vcc when not used for pwm dimming. transconductance error amplifier output. connect compensation network to achieve desired closed- 5 comp i/o loop response. led current reference input. connecting pin to vcc with 100-k series resistor sets internal reference 6 iadj i voltage to 2.42 v and the current sense threshold, v (csp-csn) to 172 mv. the pin can be modulated by external voltage source from 0 v to 2.25 v to implement analog dimming. led current report pin. the led current sensed by csp/csn input is reported as v imon = 14 i led 7 imon o r cs . bypass with a 1-nf ceramic capacitor to agnd. analog ground. return for the internal voltage reference and analog circuit. connect to circuit ground, 8 agnd ? gnd, to complete return path. current sense amplifier negative input ( ? ). connect directly to the negative node of led current sense 9 csn i resistor r cs ). current sense amplifier positive input (+). connect directly to the positive node of led current sense 10 csp i resistor r cs ). series dimming fet gate driver output. connect to gate of external n-channel mosfet or a level-shift 11 ddrv o circuit with p-channel mosfet to implement series fet pwm dimming. hysteretic overvoltage protection input. connect resistor divider from output voltage to set ovp 12 ovp i threshold and hysteresis. power ground connection pin for internal n-channel mosfet gate drivers. connect to circuit ground, 13 pgnd ? gnd, to complete return path. switch current sense input. connected to the switch current sense resistor, r is , in the source of the n- 14 is i channel mosfet. 15 gate o n-channel mosfet gate driver output. connect to gate of external switching n-channel mosfet. vcc bias supply pin. locally decouple to pgnd using a 2.2- f to 4.7- f ceramic capacitor located 16 vcc ? close to the controller. the agnd and pgnd pin must be connected to the exposed powerpad for proper operation. this powerpad ? powerpad must be connected to pcb ground plane using multiple vias for good thermal performance. copyright ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: tps92691 tps92691-q1 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 thermal pad vin ss rt/sync pwm comp iadj imon agnd vcc gate is pgnd ovp ddrv csp csn
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit vin, csp, csn ? 0.3 65 v iadj, is, pwm, rt/sync ? 0.3 8.8 v input voltage ovp, ss ? 0.3 5.5 v csp to csn (3) , pgnd ? 0.3 0.3 v vcc, gate, ddrv ? 0.3 8.8 v output voltage (4) comp ? 0.3 5.0 v imon ? 100 a source current gate, ddrv (pulsed < 20 ns) ? 500 ma sink current gate, ddrv (pulsed < 20 ns) ? 500 ma operating junction temperature, t j ? 40 140 c storage temperature, t stg 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to agnd unless otherwise noted (3) continuous sustaining voltage (4) all output pins are not specified to have an external voltage applied. 6.2 esd ratings value unit tps92691-q1 in pwp (htssop) package human-body model (hbm), per aec q100-002, all pins (1) 2000 electrostatic all pins except 1, 8, 9, and v (esd) 500 v discharge 16 charged-device model (cdm), per aec q100-011 pins 1, 8, 9, and 16 750 tps92691 in pwp (htssop) package human-body model (hbm), per ansi/esda/jedec js-001, all pins (2) 2000 electrostatic v (esd) v discharge charged-device model (cdm), per jedec specification jesd22-c101, all pins (3) 500 (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. (2) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (3) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit vin supply input voltage 6.5 14 65 v vin, crank supply input, battery crank voltage 4.5 v v csp , v csn current sense common mode 0 60 v ? sw switching frequency 80 700 khz ? sync sync frequency 0.8 ? sw 1.2 ? sw khz v iadj current reference voltage 0.14 v iadj(clamp) v t a operating ambient temperature ? 40 125 c 4 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 6.4 thermal information tps92691/-q1 thermal metric (1) pwp (htssop) unit 16 pins r ja junction-to-ambient thermal resistance 40.8 c/w r jc(top) junction-to-case (top) thermal resistance 26.1 c/w r jb junction-to-board thermal resistance 22.2 c/w jt junction-to-top characterization parameter 0.8 c/w jb junction-to-board characterization parameter 22.0 c/w r jc(bot) junction-to-case (bottom) thermal resistance 2.3 c/w (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.5 electrical characteristics t j = ? 40 c to 140 c, v in = 14 v, v iadj = 2.2 v, c vcc = 1 f, c comp = 2.2 nf, r cs = 100 m , r t = 20 k , v pwm = 5 v, no load on gate and ddrv (unless otherwise noted) (1) parameter test conditions min typ max unit input voltage (vin) v do ldo dropout voltage i cc = 20 ma, v in = 5 v 300 mv bias supply (vcc) v cc(reg) regulation voltage no load 7.0 7.5 8.0 v vcc rising threshold, v in = 8 v 4.1 4.35 v v cc(uvlo) supply undervoltage protection vcc falling threshold, v in = 8 v 3.75 4.0 v hysteresis 100 mv i cc(limit) supply current limit v cc = 0 v 26 38 46 ma i cc(stby) supply stand-by current v pwm = 0 v 1.8 2.1 ma i cc(sw) supply switching current v cc = 7.5 v, c gate = 1 nf 5.1 6.6 ma oscillator (rt/sync) r t = 40 k 165 200 230 khz ? sw switching frequency r t = 20 k 327 390 448 khz v rt rt output voltage 1 v sync rising threshold v rt/sync rising 2.7 3.1 v v sync sync falling threshold v rt/sync falling 1.8 2 v t sync(min) minimum sync clock pulse width 100 ns gate driver (gate) r gh gate driver high side resistance i gate = ? 10 ma 5.4 11.2 r gl gate driver low side resistance i gate = 10 ma 4.3 10.5 current sense (is) v is(limit) current limit threshold 497 525 550 mv t is(blank) leading edge blanking time 103 150 188 ns t is(fault) current limit fault time 35 s t ilmt(dly) is to gate propagation delay v is pulsed from 0 to 1 v 100 ns pwm comparator and slope compensation d max maximum duty cycle 90.4% 93% 94.7% v lv is to comp level shift voltage no slope compensation added 1.17 1.5 1.8 v d = d max (with max slope v sl slope compensation 200 mv compensation) i lv is level shift bias current no slope compensation added 25 a (1) all voltages are with respect to agnd unless otherwise noted copyright ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: tps92691 tps92691-q1
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com electrical characteristics (continued) t j = ? 40 c to 140 c, v in = 14 v, v iadj = 2.2 v, c vcc = 1 f, c comp = 2.2 nf, r cs = 100 m , r t = 20 k , v pwm = 5 v, no load on gate and ddrv (unless otherwise noted) (1) parameter test conditions min typ max unit d = d max (with max slope i lv + i sl is level shift source current 115 a compensation) current sense amplifier (csp, csn) cumulative offset voltage at v csp = 60 ? 40 c t j 140 c ? 5.2 5.9 mv v and v (csp-csn) = 150 mv, referred to 25 c t j 140 c ? 4.4 4.6 mv current sense input cumulative offset voltage at v csp = 60 ? 40 c t j 140 c ? 3.5 5.0 mv v and v (csp-csn) = 10 mv, referred to 25 c t j 140 c -2.8 4.0 mv current sense input v cs(offset) cumulative offset voltage at v csn = 0 ? 40 c t j 140 c ? 5.9 6.7 mv v and v (csp-csn) = 150 mv, referred to 25 c t j 140 c -4.7 5.0 mv current sense input cumulative offset voltage at v csn = 0 ? 40 c t j 140 c ? 2.3 3.2 mv v and v (csp-csn) = 10 mv, referred to 25 c t j 140 c ? 1.7 2.6 mv current sense input cs (bw) current sense unity gain bandwidth 500 khz i cs(bias) csp, csn bias current v csp, csn = 60 v 4 a current monitor (imon) v imon(clp) imon output voltage clamp 3.2 3.7 4.2 v v imon(os) imon buffer offset voltage ? 11.4 ? 1.6 7.3 mv analog adjust (iadj) v iadj(clp) iadj internal clamp voltage i iadj = 1 a 2.27 2.42 2.55 v i iadj(bias) iadj input bias current v iadj < 2.2 v 90 na r iadj(lmt) iadj current limiting series resistor v iadj > 2.6 v 12 k error amplifier (comp) g m transconductance 121 a/v i comp(src) comp current source capacity v iadj = 1.4 v, v (csp-csn) = 0 v 130 a i comp(sink) comp current sink capacity v iadj = 0 v, v (csp-csn) = 0.1 v 130 a ea (bw) error amplifier bandwidth ? 3 db 5 mhz v comp(rst) comp pin reset voltage 100 mv r comp(dch) comp discharge fet resistance 246 soft-start (ss) i ss soft-start source current 7 10 12.8 a v ss(rst) soft-start pin reset voltage 25 mv r ss(dch) ss discharge fet resistance 260 overvoltage protection (ovp) v ovp(thr) ovp detection threshold 1.18 1.24 1.31 v i ovp(hys) ovp hysteresis current 12 20 27.5 a pwm input (pwm) schmitt trigger logic level (high v pwm(high) 2.5 2.7 v threshold) schmitt trigger logic level (low v pwm(low) 2.0 2.3 v threshold) r pwm(pd) pwm pulldown resistance 1 m t dly(rise) pwm to ddrv rising delay 54 ns t dly(fall) pwm to ddrv falling delay 72 ns pwm gate drive output (ddrv) r dh ddrv high-side resistance 6.1 12.8 r dl ddrv low-side resistance 5.2 11.4 6 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 electrical characteristics (continued) t j = ? 40 c to 140 c, v in = 14 v, v iadj = 2.2 v, c vcc = 1 f, c comp = 2.2 nf, r cs = 100 m , r t = 20 k , v pwm = 5 v, no load on gate and ddrv (unless otherwise noted) (1) parameter test conditions min typ max unit thermal shutdown thermal shutdown temperature 175 c thermal shutdown hysteresis 25 c 6.6 typical characteristics t a = 25 c, v in = 14 v, v iadj = 2.2 v, c vcc = 1 f, c comp = 2.2 nf, r cs = 100 m , r t = 20 k , v pwm = 5 v, no load on gate and ddrv (unless otherwise noted) figure 1. vcc regulation voltage vs temperature figure 2. standby current vs temperature figure 3. vcc dropout voltage vs temperature figure 4. uvlo threshold vs temperature copyright ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: tps92691 tps92691-q1 temperature (c) vcc regulation voltage (v) -40 -20 0 20 40 60 80 100 120 140 7.2 7.3 7.4 7.5 7.6 7.7 7.8 d001 temperature (c) i vcc(stby) (ma) -40 -20 0 20 40 60 80 100 120 140 1.7 1.725 1.75 1.775 1.8 1.825 1.85 1.875 1.9 d018 temperature (c) vcc dropout voltage (mv) -40 -20 0 20 40 60 80 100 120 140 100 200 300 400 500 600 d002 v in = 5v, i vcc = 20ma temperature (c) uvlo (v) -40 -20 0 20 40 60 80 100 120 140 3.85 3.9 3.95 4 4.05 4.1 4.15 4.2 4.25 d003 rising threshold falling threshold
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com typical characteristics (continued) t a = 25 c, v in = 14 v, v iadj = 2.2 v, c vcc = 1 f, c comp = 2.2 nf, r cs = 100 m , r t = 20 k , v pwm = 5 v, no load on gate and ddrv (unless otherwise noted) figure 5. vcc current limit vs temperature figure 6. r t vs switching frequency figure 7. switching frequency vs temperature figure 8. maximum duty cycle vs temperature figure 9. is current limit threshold vs temperature figure 10. leading edge blanking period vs temperature 8 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 temperature (c) is current limit threshold (mv) -40 -20 0 20 40 60 80 100 120 140 518 520 522 524 526 528 530 532 d007 temperature (c) leb period (ns) -40 -20 0 20 40 60 80 100 120 140 148 150 152 154 156 158 d008 temperature (c) switching frequency (khz) -40 -20 0 20 40 60 80 100 120 140 382 386 390 394 398 402 d006 temperature (c) d max (%) -40 -20 0 20 40 60 80 100 120 140 92.7 92.8 92.9 93 93.1 93.2 d012 temperature (c) vcc current limit (ma) -40 -20 0 20 40 60 80 100 120 140 37 37.5 38 38.5 39 39.5 d004 frequency (khz) r t (k : ) 50 150 250 350 450 550 650 750 10 20 30 40 50 60 70 80 100 d005
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 typical characteristics (continued) t a = 25 c, v in = 14 v, v iadj = 2.2 v, c vcc = 1 f, c comp = 2.2 nf, r cs = 100 m , r t = 20 k , v pwm = 5 v, no load on gate and ddrv (unless otherwise noted) v iadj = 2.1 v v iadj = 2.1 v figure 11. v (csp-csn) threshold vs v csp figure 12. current sense amplifier offset vs temperature figure 13. csp/csn input bias current vs temperature figure 14. v imon vs v (csp-csn) figure 15. v (csp-csn) threshold vs v iadj figure 16. v iadj voltage clamp vs temperature copyright ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: tps92691 tps92691-q1 v (csp-csn) (mv) v imon (v) 0 30 60 90 120 150 180 210 240 270 300 0 0.5 1 1.5 2 2.5 3 3.5 4 d011 v csp (v) v (csp-csn) threshold (mv) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 149.4 149.6 149.8 150 150.2 150.4 150.6 150.8 151 d009 temperature (c) v cs(offset) (mv) -40 -20 0 20 40 60 80 100 120 140 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 d010 v csp = 60v v csp = 0v v iadj (v) v (csp-csn) threshold (mv) 0 0.28 0.56 0.84 1.12 1.4 1.68 1.96 2.24 2.52 2.8 3 0 20 40 60 80 100 120 140 160 180 200 d014 temperature (c) v iadj voltage clamp (v) -40 -20 0 20 40 60 80 100 120 140 2.4 2.405 2.41 2.415 2.42 2.425 2.43 2.435 2.44 d015 temperature (c) csp, csn bias current ( p a) -40 -20 0 20 40 60 80 100 120 140 3.8 3.85 3.9 3.95 4 4.05 4.1 4.15 4.2 d013
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com typical characteristics (continued) t a = 25 c, v in = 14 v, v iadj = 2.2 v, c vcc = 1 f, c comp = 2.2 nf, r cs = 100 m , r t = 20 k , v pwm = 5 v, no load on gate and ddrv (unless otherwise noted) figure 17. ovp detection threshold vs temperature figure 18. ovp hysteresis current vs temperature 10 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 temperature (c) ovp detection threshold (v) -40 -20 0 20 40 60 80 100 120 140 1.22 1.225 1.23 1.235 1.24 1.245 1.25 1.255 1.26 d016 temperature (c) ovp hysteresis current ( p a) -40 -20 0 20 40 60 80 100 120 140 19 19.4 19.8 20.2 20.6 21 d017
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 7 detailed description 7.1 overview the tps92691/-q1 wide input range (4.5 v to 65 v) controller features all of the functions necessary to implement a highly efficient and compact led driver based on step-up or step-down converter topologies. the device implements a fixed-frequency, peak current mode control technique to achieve a constant current output, ideal for driving a single string of series-connected leds. the integrated low input offset, rail-to-rail current sense amplifier supports a wide range of output voltages (0 v to 65 v) and is capable of powering an led string consisting of 1 to more than 20 white leds. the controller is compatible with either high- or low-side current shunt sensing technique, based on the led configuration and driver topology. the led current sense threshold, set by the analog adjust input, iadj, provides the capability to analog (amplitude) dim over a linear range of 15:1 by varying the voltage, v iadj , from 140 mv to 2.25 v. the iadj input provides the means to externally program led current and facilitates calibration, brightness correction, and thermal management of the leds. high resolution and linear dimming response is achieved by varying the duty cycle of led current based on the pwm input. the pwm input directly controls the gate and ddrv drive outputs, controls the internal oscillator, and enables high-speed pwm dimming with over 1000:1 contrast ratio when using an external mosfet placed in series with the led load. the current monitor output, imon, reports the instantaneous status of led current measured by the rail-to-rail current sense amplifier. this feature is incorporated to indicate led short and open- circuit failures and enables cable harness fault detection independent of led driver topology. other fault protection features include cycle-by-cycle current limiting, hysteresis-based overvoltage protection, vcc undervoltage protection, thermal shutdown, and remote shutdown capability by pulling down the ss pin. 7.2 functional block diagram copyright ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: tps92691 tps92691-q1 q s r standby 7.5v ldo regulator uvlo (4.1v) thermal limit internal references 1.24v clock oscillator & slope + + + ss slope max duty 10 a + + 525mv leb leb + 1.24v 35 s timer 10 a 20 a fault vcc pgnd vin rt/ sync ss pwm comp csp csn imon iadj agnd pgnd gate vcc ovp is ddrv standby 138k 2k fault pwm comp 3.7v 2.42v 525mv + 2.42v 12k fault reset logic 25mv 100mv slope current sense amplifier gain = 14
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com 7.3 feature description 7.3.1 internal regulator and undervoltage lockout (uvlo) the ic incorporates a 65-v input v in rated linear regulator to generate the 7.5 v (typ) v cc bias supply and other internal reference voltages. the v cc output is monitored to implement uvlo protection. the device is enabled when v cc exceeds the 4.1-v (typ) threshold and is disabled when v cc drops below the 4.0-v (typ) threshold. the uvlo comparator provides 0.1 v of hysteresis to avoid chatter during transitions. the uvlo thresholds are internally fixed and cannot be adjusted. the supply current, i cc , is limited to 26 ma minimum to protect the device under vcc pin short-circuit conditions. the v cc supply powers the internal circuitry and n-channel gate driver outputs, gate, and ddrv. place a bypass capacitor in the range of 2.2 f to 4.7 f across the v cc output and pgnd to ensure proper operation. the regulator operates in dropout when input voltage v in falls below 7.5 v forcing v cc to be lower than v in by 300 mv for a 20-ma supply current. the v cc is a regulated output of the internal regulator and is not recommended to be driven from an external power supply. 7.3.2 oscillator the tps92691/-q1 switching frequency is programmable by a single external resistor connected between the rt/sync pin and the agnd pin. to set a desired frequency, ? sw (hz), the resistor value can be calculated from equation 1 . (1) figure 6 shows a graph of switching frequency versus resistance, r t . ti recommends a switching frequency setting between 80 khz and 700 khz for optimal performance over input and output voltage operating range and for best efficiency. operation at higher switching frequencies requires careful selection of n-channel mosfet characteristics and should take into consideration additional switching losses and junction temperature rise. figure 19. oscillator synchronization through ac coupling the internal oscillator can be synchronized by ac coupling an external clock pulse to rt/sync pin as shown in figure 19 . the positive going synchronization clock at the rt pin must exceed the rt sync threshold and the negative going synchronization clock at the rt pin must exceed the rt sync falling threshold to trip the internal synchronization pulse detector. ti recommends that the frequency of the external synchronization pulse is within 20% of the internal oscillator frequency programmed by the r t resistor. ti recommends a minimum coupling capacitor of 100 nf and typical pulse width of 100 ns for proper synchronization. in the case where external synchronization clock is lost the internal oscillator takes control of the switching rate based on the r t resistor to maintain output current regulation. the r t resistor is always required whether the oscillator is free running or externally synchronized. 7.3.3 gate driver the tps92691/-q1 contains a n-channel gate driver that switches the output v gate between v cc and pgnd. a peak source and sink current of 500 ma allows controlled slew-rate of the mosfet gate and drain node voltages, limiting the conducted and radiated emi generated by switching. the gate driver supply current i cc(gate) depends on the total gate drive charge (q g ) of the mosfet and the operating frequency of the converter, ? sw , . ti recommends a mosfet with a low gate charge specification to limit the junction temperature rise and switch transition losses. 12 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 cc(gate) g sw i q f u rt/sync tps92691 t r sync c oscillator clock 10 t 1.047 sw 1.432 10 r f u :
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 feature description (continued) while choosing the n-channel mosfet device, consider the threshold voltage when operating in the dropout region when v in is below the v cc regulation level. ti recommends a logic level device with a threshold voltage below 5 v when the device is required to operate at an input voltage less than 7 v. 7.3.4 rail-to-rail current sense amplifier the internal rail-to-rail current sense amplifier measures the average led current based on the differential voltage drop between the csp and csn inputs over a common mode range of 0 v to 65 v. the differential voltage, v (csp-csn) , is amplified by a voltage-gain factor of 14 and is connected to the negative input of the transconductance error amplifier. accurate led current feedback is achieved by limiting the cumulative input offset voltage, (represented by the sum of the voltage-gain error, the intrinsic current sense offset voltage, and the transconductance error amplifier offset voltage) to less than 5 mv over the recommended common-mode voltage, and temperature range. figure 20. current sense amplifier input filter options an optional common-mode or differential mode low-pass filter implementation, as shown in figure 20 , can be used to smooth out the effects of large output current ripple and switching current spikes caused by diode reverse recovery. ti recommends a filter resistance in the range of 10 to 100 to limit the additional offset caused by amplifier bias current and achieve best accuracy and line regulation. 7.3.5 transconductance error amplifier the internal transconductance amplifier generates an error signal proportional to the difference between the led current sense feedback voltage and the external iadj input voltage. closed-loop regulation is achieved by connecting a compensation network to the output of the error amplifier. in most led driver applications, a stable response can be achieved by connecting a capacitor across the comp output and ground to implement a simple integral compensator. ti recommends a capacitor value between 10 nf and 100 nf as a good starting point. higher closed-loop bandwidth can be achieved by implementing a proportional-integral compensator consisting of a series resistor and a capacitor network connected across the comp output and ground. based on the converter topology, the compensation network should be tuned to achieve a minimum of 60 of phase margin and 10 db of gain margin. the application and implementation section presents detailed equations. 7.3.6 switch current sense and internal slope compensation the main mosfet current is monitored by the is input pin to implement peak current mode control. the gate output duty cycle is derived by comparing the peak switch current, measured by the r is resistor, to the internal comp voltage threshold. an internal slope signal is added to the measured sense voltage, v is , to prevent subharmonic oscillations for duty cycles greater than 50%. the linear slope voltage, v sl , of fixed amplitude 200 mv, is derived from a 100- a sawtooth ramp current synchronized to the internal oscillator frequency. an internal blanking circuit prevents mosfet switching current spike propagation and premature termination of duty cycle by internally shunting the is input for 150 ns after the beginning of the new switching period. ti recommends an external low-pass rc filter with resistor values ranging from 100 to 500 for additional noise suppression when operating in the dropout region (v in less than 7 v). copyright ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: tps92691 tps92691-q1 csp csn fdm c fs r fs r fcm c fcm c + cs r tps92691 common mode filter capacitors differential mode filter capacitors
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com feature description (continued) cycle-by-cycle current limit is accomplished by a redundant internal comparator, which immediately terminates the gate output when the is input voltage, v is , exceeds 525-mv (typ) threshold. upon a current limit event, the ss and comp pin are internally grounded to reset the state of the controller. the gate output is enabled after the expiration of the 35- s internal fault timer and a new start-up sequence is initiated through the ss pin. 7.3.7 analog adjust input the voltage across the led current sense resistor, v (csp ? csn) , is regulated to the analog adjust input voltage, v iadj , scaled by the current sense amplifier voltage gain of 14. the led current can be linearly adjusted by varying the voltage on iadj from 140 mv to 2.25 v using either a resistor divider from v cc or a voltage source. the iadj pin can be connected to v cc through an external resistor to set led current based on the 2.42-v internal reference voltage. figure 21 shows different methods to set the iadj voltage. the iadj input can be used in conjunction with a ntc resistor to implement thermal foldback protection as shown in figure 21 (b). a pwm signal in conjunction with first- or second-order low-pass filter can be used to program the iadj voltage as shown in figure 21 (c). a. static reference setting resistor divider from vcc b. thermal fold-back circuit using external ntc resistor c. analog dimming achieved by low-pass filtering external pwm signal figure 21. setting analog adjust input voltage 7.3.8 pwm input and series dimming fet gate driver output the tps92691/-q1 incorporates a dimming input (pwm) for pulse-width modulating the output led current. the brightness of the leds can be linearly varied by modulating the duty cycle of the pulsating voltage source connected to the pwm input pin. driving the pwm input below 2.3 v (typ) turns off switching, parks the oscillator, disconnects the comp pin, and sets the ddrv output to gnd in order to maintain the charge on the compensation network and output capacitors. on the rising edge of the pwm input voltage (v pwm > 2.5 v), the gate and ddrv outputs are enabled to ramp the inductor current to the previous steady-state value. the comp pin is connected and the error amplifier and oscillator are enabled only when the switch current sense voltage v is exceeds the comp voltage, v comp , thus immediately forcing the converter into steady-state operation with minimum led current overshoot. the pwm pin should be connected to the v cc if dimming is not required. an internal pulldown resistor sets the input to logic-low and disables the part when the pin is disconnected or left floating. 14 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 iadj tps92691 adj1 r adj2 r vcc iadj tps92691 ntc r adj r vcc ? w? iadj tps92691 adj c adj r pwm signal (a) (b) (c)
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 feature description (continued) figure 22. series dimming fet connections the ddrv output follows the pwm input signal and is capable of sinking and sourcing up to 500 ma of peak current to control a low-side series connected n-channel dimming fet. alternatively, the ddrv output can be translated with an external level-shift circuit to drive a high-side series p-channel dimming fet as shown in figure 22 . the series dimming fet is required to achieve high contrast ratio as it ensures fast rise and fall times of the led current in response to the pwm input. without any dimming fet, the rise and fall times are limited by the inductor slew rate and the closed-loop bandwidth of the system. leave the ddrv pin unconnected if not used. 7.3.9 soft-start the soft-start feature helps the regulator gradually reach the steady-state operating point, thus reducing startup stresses and surges. the tps92691/-q1 clamps the comp pin to the ss pin, separated by a diode, until led current nears the regulation threshold. the internal 10- a soft-start current source gradually increases the voltage on an external soft-start capacitor c ss connected to the ss pin. this results in a gradual rise of the comp voltage from gnd. the internal 10- a current source turns on when vcc exceeds the uvlo threshold. at the beginning of the soft- start sequence, the ss pulldown switch is active and is released when the voltage v ss drops below 25 mv. the ss pin can also be pulled down by an external switch to stop switching. when the ss pin is externally driven to enable switching, the slew-rate on the comp pin should be controlled by choosing a compensation capacitor that avoids large startup transients. the value of c ss should be large enough to charge the output capacitor during the soft-start transition period. 7.3.10 current monitor output the imon pin voltage represents the led current measured by the rail-to-rail current sense amplifier across the external current shunt resistor. the linear relationship between the imon voltage and led current includes the amplifier gain-factor of 14 (see figure 14 ). the imon output can be connected to an external microcontroller or comparator to facilitate led open, short, or cable harness fault detection and mitigation based on programmable threshold v octh . the imon voltage is internally clamped to 3.7 v. figure 23. led overcurrent protection using imon output copyright ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: tps92691 tps92691-q1 + imon tps92691 pwm ss v octh led+ ddrv tps92691 ddrv tps92691 led-
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com feature description (continued) 7.3.11 overvoltage protection the tps92691/-q1 device includes a dedicated ovp pin which can be used for either input or output overvoltage protection. this pin features a precision 1.24 v (typ) threshold with 20- a (typ) of hysteresis current. the overvoltage threshold limit is set by a resistor divider network from the input or output terminal to gnd. when the ovp pin voltage exceeds the reference threshold, the gate and ddrv pins are immediately pulled low and the ss and comp capacitors are discharged. the gate is enabled and a new startup sequence is initiated after the voltage drops below the hysteresis threshold set by the 20- a source current and the external resistor divider. 7.3.12 thermal protection internal thermal shutdown circuitry is implemented to protect the controller in the event the maximum junction temperature is exceeded. when activated, typically at 175 c, the controller is forced into a shutdown mode, disabling the internal regulator. this feature is designed to prevent overheating and damage to the device. 7.4 device functional modes this device has no additional functional modes. 16 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps92691/-q1 controller is suitable for implementing step-up or step-down led driver topologies including buck, boost, buck-boost, sepic, cuk, and flyback. use the following design procedure to select component values for the tps92691/-q1 device. this section presents a simplified discussion of the design process for the buck, boost, and buck-boost converter. the expressions derived for buck-boost can also be altered to select components for a 1:1 coupled-inductor sepic converter. the design procedure can be easily adapted for flyback and cuk converter topologies. figure 24. boost led driver figure 25. sepic led driver copyright ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: tps92691 tps92691-q1 tps92691-q1 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 led+ led ? vin ss rt/sync pwm comp iadj imon agnd pad vcc gate is pgnd ovp ddrv csp csn vin c ss c comp r t c imon c in r is q 1 c vcc r ov1 r ov2 r cs q 2 d c out c ov c s l 1 l 2 r adj2 r adj1 v pwm tps92691-q1 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vin led+ led ? vin ss rt/sync pwm comp iadj imon agnd pad vcc gate is pgnd ovp ddrv csp csn l r ov1 r ov2 r is r cs q 2 q 1 d c ss c comp r t c imon c out c vcc c in c ov r adj2 r adj1 v pwm
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com application information (continued) figure 26. buck-boost led driver figure 27. buck led driver 18 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 tps92691-q1 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vin led+ led ? vin ss rt/sync pwm comp iadj imon agnd pad vcc gate is pgnd ovp ddrv csp csn c ss c comp r t c imon r adj2 r adj1 l r is q 1 c vcc c in r ov1 r ov2 r cs q 2 c out c ov r ls2 r ls1 q 3 d q 4 v pwm tps92691-q1 12 3 4 5 6 7 8 16 15 14 13 12 11 10 9 led+ led ? vin ss rt/sync pwm comp iadj imon agnd pad vcc gate is pgnd ovp ddrv csp csn r ov1 r ov2 r cs q 2 q 1 d c out c ov vin c ss c comp r t c imon c in r ls2 r ls1 l r is q 1 c vcc q 3 q 4 r adj2 r adj1 v pwm
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 application information (continued) 8.1.1 duty cycle considerations the switch duty cycle, d, defines the converter operation and is a function of the input and output voltages. in steady state, the duty cycle is derived using expression: buck: (2) boost: (3) buck-boost: (4) the minimum duty cycle, d min , and maximum duty cycle, d max , are calculated by substituting maximum input voltage, v in(max) , and the minimum input voltage, v in(min) , respectively in the previous expressions. the minimum duty cycle achievable by the device is determined by the leading edge blanking period and the switching frequency. the maximum duty cycle is limited by the internal oscillator to 93% (typ) to allow for minimum off-time. it is necessary for the operating duty cycle to be within the operating limits of the device to ensure closed-loop led current regulation over the specified input and output voltage range. 8.1.2 inductor selection the inductor peak-to-peak ripple current, i l-pp , is typically set between 10% and 80% of the maximum inductor current, i l , as a good compromise between core loss and copper loss of the inductor. higher ripple inductor current allows a smaller inductor size, but places more of a burden on the output capacitor to smooth the led current ripple. knowing the desired ripple ratio rr, switching frequency ? sw , maximum duty cycle d max , and the typical led current i led , the inductor value can be calculated as follows: buck: (5) (6) boost and buck-boost: (7) (8) as an alternative, the inductor can be selected based on ccm-dcm boundary condition specified based on output power, p o(bdry) . the choice of inductor ensures ccm operation in battery-powered led driver applications that are designed to support different led string configurations with a wide range of programmable led current setpoints. the output power should be calculated based on the lowest led current and the lowest output voltage requirements for a given application. (9) buck: (10) boost: copyright ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: tps92691 tps92691-q1 o in o v d v v o in o v v d v o in v d v 2 o(max) o(max) o(bdry) sw in v v l 1 2 p f v u ? ? u u ? 1 o(bdry) led(min) o(min) p i v d u in(min) max l(pp) sw v d l i f u ' u led l(pp) l max i i rr i rr 1 d ' ? ? in(min) o max l(pp) sw v v d l i f u ' u l(pp) l led i rr i rr i ' ? ?
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com application information (continued) (11) buck-boost: (12) the saturation current rating of the inductor should be greater than the peak inductor current, i l(pk) , at the maximum operating temperature. (13) 8.1.3 output capacitor selection the output capacitors are required to attenuate the discontinuous or large ripple current generated by switching and achieve the desired peak-to-peak led current ripple, i led(pp) . the capacitor value depends on the total series resistance of the led string, r d , the switching frequency, ? sw , and on the converter topology (that is, step- up or step-down). for the buck and cuk topology, the inductor is in series with led load and requires a smaller capacitor than the boost, buck-boost, and sepic topologies to achieve the same led ripple current. the capacitance required for the target led ripple current can be calculated based on following equations. buck: (14) boost and buck-boost: (15) when choosing the output capacitors, it is important to consider the esr and the esl characteristics as they directly impact the led current ripple. ceramic capacitors are the best choice due to their low esr, high ripple current rating, long lifetime, and good temperature performance. when selecting ceramic capacitors, it is important to consider the derating factors associated with higher temperature and dc bias operating conditions. ti recommends an x7r dielectric with voltage rating greater than maximum led stack voltage. an aluminum electrolytic capacitor can be used in parallel with ceramic capacitors to provide bulk energy storage. the aluminum capacitors must have necessary rms current and temperature ratings to ensure prolonged operating lifetime. the minimum allowable rms output capacitor current rating, i cout(rms) , can be approximated: buck: (16) boost and buck-boost: (17) the expressions ( equation 14 to equation 17 ) are best suited for designs driving a fixed led load, with known output voltage and led current. for applications that are required to support different led string configurations with a wide range of programmable led current setpoints, the previous expressions are rearranged to reflect output capacitance based on the maximum output power, p o(max) , to ensure that led current ripple specifications are met over the entire range of operation. typical buck-boost led driver provides the details for buck-boost led driver. 20 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 max cout(rms) led max d i i 1 d u led(pp) cout(rms) i i 12 ' led max out sw d led(pp) i d c f r i u u u ' l(pp) out sw d led(pp) i c 8 f r i ' u u u ' in(min) max l(pk) l sw v d i i 2 l f u u u 2 o(bdry) sw o(max) in 1 l 1 1 2 p f v v u u u ? ? ? 1 2 in in o(bdry) sw o(max) v v l 1 2 p f v u ? ? u u ? 1
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 application information (continued) 8.1.4 input capacitor selection the input capacitors, c in , smooth the input voltage ripple and store energy to supply input current during input voltage or pwm dimming transients. the series inductor in the boost, sepic, and cuk topology provides continuous input current and requires a smaller input capacitor to achieve desired input ripple voltage, v in(pp) . the buck and buck-boost topology have discontinuous input current and require a larger capacitor to achieve the same input voltage ripple. based on the switching frequency, ? sw , and the maximum duty cycle, d max , the input capacitor value can be calculated as follows: buck: (18) boost: (19) buck-boost: (20) x7r dielectric-based ceramic capacitors are the best choice due to their low esr, high ripple current rating, and good temperature performance. for applications using pwm dimming, ti recommends an aluminum electrolytic capacitor in addition to ceramic capacitors to minimize the voltage deviation due to large input current transients generated in conjunction with the rising and falling edges of the led current. figure 28. vin filter for most applications, ti highly recommends to bypass the vin pin with a 0.1- f ceramic capacitor placed as close as possible to the device and add a series 10- resistor to create a 150-khz low-pass filter and eliminate undesired high-frequency noise. 8.1.5 main power mosfet selection the power mosfet should be able to sustain the maximum switch node voltage, v sw , and switch rms current derived based on the converter topology. ti recommends a drain voltage v ds rating of at least 20% greater than the maximum switch node voltage to ensure safe operation. the mosfet drain-to-source breakdown voltage, v ds , and rms current ratings are calculated using the following expressions. buck: (21) (22) boost: (23) copyright ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: tps92691 tps92691-q1 q(rms) led max i i d u ds in(max) v v 1.2 u vin tps92691 vin c vin r led max in sw in(pp) i d c f v u u ' l(pp) in sw in(pp) i c 8 f v ' u u ' led max max in sw in(pp) i d (1 d ) c f v u u u ' ds o(ov) v v 1.2 u
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com application information (continued) (24) buck-boost: (25) (26) where the voltage, v o(ov) , is the overvoltage protection threshold and the worst-case output voltage under fault conditions. select a mosfet with low total gate charge, q g , to minimize gate drive and switching losses. the mosfet r ds resistance is usually a less critical parameter because the switch conduction losses are not a significant part of the total converter losses at high operating frequencies. the switching and conduction losses are calculated as follows: (27) (28) c rss is the mosfet reverse transfer capacitance. i l is the average inductor current. i gate is gate drive output current, typically 500 ma. the mosfet power rating and package should be selected based on the total calculated loss, the ambient operating temperature, and maximum allowable temperature rise. 8.1.6 rectifier diode selection a schottky diode (when used as a rectifier) provides the best efficiency due to low forward voltage drop and near-zero reverse recovery time. ti recommends a diode with a reverse breakdown voltage, v d(br) , greater than or equal to mosfet drain-to-source voltage, v ds , for reliable performance. it is important to understand the leakage current characteristics of the schottky diode, especially at high operating temperatures because it impacts the overall converter operation and efficiency. the current through the diode, i d , is given by: (29) the diode should be sized to exceed the current rating, and the package should be able to dissipate power without exceeding the maximum allowable temperature. 8.1.7 led current programming the led current is set by the external current sense resistor, r cs , and the analog adjust voltage, v iadj . the current sense resistor is placed in series with the led load and can be located either on the high side (connected to the output, v o ), or on the low side (connected to ground, gnd). the csp and csn inputs of the internal rail-to-rail current sense amplifier are connected to the r cs resistor to enable closed-loop regulation. when v iadj > 2.5 v, the internal 2.42-v reference sets the v (csp-csn) threshold to 172 mv and the led current is regulated to: (30) the led current can be programmed by varying v iadj between 140 mv to 2.25 v. the led current can be calculated using: (31) 22 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 max q(rms) led max d i i 1 d u ds in(max) o(ov) v v v 1.2 u iadj led cs v i 14 r u led cs 0.172 i r d l m a x i i (1 d ) u 2 l sw rss sw sw gate i v c f p i u u u 2 cond ds q(rms) p r i u
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 application information (continued) the output voltage ripple should be limited to 50 mv for best performance. ti recommends a low-pass common- mode filter consisting of 10- resistors is series with csp and csn inputs and 0.01- f capacitors to ground to minimize the impact of voltage ripple and noise on led current accuracy (see figure 20 ). a 0.1- f capacitor across csp and csn is included to filter high-frequency differential noise. 8.1.8 switch current sense resistor and slope compensation the switch current sense resistor, r is , is used to implement peak current mode control and to set the peak switch current limit. the value of switch current sense r is is selected to achieve stable inner current loop operation based on the magnitude of slope compensation ramp, v sl , and to protect the main switching mosfet under fault conditions. the lower of the two values calculated using the following equations should be selected for r is . (32) (33) the internal slope compensation voltage, v sl is fixed at 200 mv (typ). a resistor can be placed in series with the is pin to increase slope compensation, if necessary. the peak switch current limit is set based on the internal current limit threshold of 525 mv (typ) and adjusted based on slope compensation to ensure reliable operation while pwm dimming. figure 29. is input filter the use of a 1-nf and 100- low-pass filter is optional. if used, the resistor value should be less than 500 to limit its influence on the internal slope compensation signal. 8.1.9 feedback compensation the open-loop response is the product of the modulator transfer function (shown in equation 34 ) and the feedback transfer function. using a first-order approximation, the modulator transfer function can be modeled as a single pole created by the output capacitor, and in the boost and buck-boost topologies, a right half-plane zero created by the inductor, where both have a dependence on the led string dynamic resistance, r d . because ti recommends a ceramic capacitor, the esr of the output capacitor is neglected in the analysis. the small-signal modulator model also includes a dc gain factor that is dependent on the duty cycle, output voltage, and led current. (34) table 1 summarizes the expression for the small-signal model parameters. copyright ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: tps92691 tps92691-q1 z led 0 comp p s 1 ? i g ? v s 1 ? z ? 1 ? z ? 1 vcc gate is pgnd tps92691 is r 100 o 1 nf is(limit) sl max is l(pk) v v d r i u sl sw is o(max) 2 v l f r v u u u
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com application information (continued) the feedback transfer function includes the current sense resistor and the loop compensation of the transconductance amplifier. a compensation network at the output of the error amplifier is used to configure loop gain and phase characteristics. a simple capacitor, c comp , from comp to gnd (as shown in figure 30 ) provides integral compensation and creates a pole at the origin. alternatively, a network of r comp , c comp , and c hf , shown in figure 31 , can be used to implement proportional and integral (pi) compensation and to create a pole at the origin, a low-frequency zero, and a high-frequency pole. table 1. small-signal model parameters dc gain (g 0 ) pole frequency ( p ) zero frequency ( z ) buck 1 ? boost buck-boost the feedback transfer function is defined as follows. feedback transfer function with integral compensation: (35) feedback transfer function with proportional integral compensation: (36) the pole at the origin minimizes output steady-state error. high bandwidth is achieved with the pi compensator by placing the low-frequency zero an order of magnitude less than the crossover frequency. use the following expressions to calculate the compensation network. figure 30. integral compensation figure 31. proportional-integral compensation buck with integral compensator: (37) boost and buck-boost with proportional integral compensator: 24 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 o is o d led (1 d) v r v d r i u u u u o d led o d out v d r i v r c u u u u 2 o led v (1 d) d l i u u u o is o d led (1 d) v r v r i u u u o d led o d out v r i v r c u u u 2 o led v (1 d) l i u u 3 cs comp p 8.75 10 r c u u z d out 1 r c u + + comp csp csn iadj + current sense amplifier gain = 14 r cs i led vcc 2.42v c comp tps92691 + + comp csp csn iadj + current sense amplifier gain = 14 r cs i led vcc 2.42v c hf tps92691 c comp r comp comp comp comp m cs comp hf led comp hf comp comp hf ? 1 s r c v 14 g r ? s c c i c c 1 s r c c u u u u u u u u ? ? ? ? 1 ? 1 comp m cs comp led ? v 14 g r ? s c i u u u
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 (38) (39) (40) the loop response is verified by applying step input voltage transients. the goal is to minimize led current overshoot and undershoot with a damped response. additional tuning of the compensation network may be necessary to optimize pwm dimming performance. 8.1.10 soft-start the soft-start time (t ss ) is the time required for the led current to reach the target setpoint. the required soft- start time, t ss , is programmed using a capacitor, c ss , from ss pin to gnd, and is based on the led current, output capacitor, and output voltage. (41) 8.1.11 overvoltage protection the overvoltage threshold is programmed using a resistor divider, r ov2 and r ov1 , from the output voltage, v o , to ground for boost and sepic topologies, as shown in figure 24 and figure 25 . if the leds are referenced to a potential other than ground, as in the buck-boost or buck configuration, the output voltage is sensed and translated to ground by using a pnp transistor and level-shift resistors, as shown in figure 27 and figure 26 . the overvoltage turn-off threshold, v o(ov) , is: boost: (42) buck and buck-boost: (43) the overvoltage hysteresis, v ov(hys) is: (44) 8.1.12 pwm dimming considerations when pwm dimming, the tps92691/-q1 requires another mosfet placed in series with the led load. this mosfet should have a voltage rating greater than the output voltage, v o , and a current rating at least 10% higher than the nominal led current, i led . it is important to control the slew-rate of the external fet to achieve a damped led current response to pwm rising-edge transitions. for a low-side, n-channel dimming fet, the slew-rate is controlled by placing a resistor in series with the gate pin. the rise and fall times depend on the value of the resistor and the gate-to-source capacitance of the mosfet. the series resistor can be bypassed with a diode for fast rise time and slow fall times to achieve 100:1 or higher contrast ratios. if a high-side p-channel dimming fet is used, the rise and fall times can be controlled by selecting appropriate resistors for the level-shift network, r ls1 and r ls2 , as shown in figure 26 . copyright ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: tps92691 tps92691-q1 6 out out ss ss led c v c 12.5 10 t i u u ? ? 1 comp p comp 1 r c z u comp hf c c 100 3 cs 0 comp z r g c 8.75 10 u u u ? z ? 1 ov(hys) ovp(hys) ov2 v i r u ov2 o(ov) ovp(thr) ov1 r v v 0.7 r u ov1 ov2 o(ov) ovp(thr) ov1 r r v v r u ? ? 1
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com 8.2 typical applications 8.2.1 typical boost led driver figure 32. boost led driver with high-side current sense 26 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 8.2.1.1 design requirements table 2 shows the design parameters for the boost led driver application. table 2. design parameters parameter test conditions min typ max unit input characteristics input voltage range 7 14 18 v input uvlo setting 4.5 v output characteristics led forward voltage 3.2 v number of leds in series 12 v o output voltage led+ to led ? 38.4 v i led output current 500 ma rr led current ripple ratio 5% r d led string resistance 4 maximum output power 20 25 w pwm dimming range 240-hz pwm frequency 4% 100% systems characteristics i l(pp) inductor current ripple 20% v in(pp) input voltage ripple 70 mv v o(ov) output overvoltage protection threshold 50 v v ov(hys) output overvoltage protection hysteresis 5 v t ss soft-start period 8 ms switching frequency 390 khz 8.2.1.2 detailed design procedure this procedure is for the boost led driver application. 8.2.1.2.1 calculating duty cycle solve for d, d max , and d min : (45) (46) (47) 8.2.1.2.2 setting switching frequency solve for r t : (48) the closest standard resistor of 20 k is selected. 8.2.1.2.3 inductor selection the inductor value should ensure continuous conduction mode (ccm) of operation and should achieve desired ripple specification, i l(pp) . copyright ? 2015, texas instruments incorporated submit documentation feedback 27 product folder links: tps92691 tps92691-q1 10 10 3 t 1.047 1.047 3 sw 1.432 10 1.432 10 r 20.05 10 f 390 10 u u u u o in(max) min o v v 38.4 18 d 0.5312 v 38.4 o in(min) max o v v 38.4 7 d 0.8177 v 38.4 o in o v v 38.4 14 d 0.6354 v 38.4
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com (49) solving for inductor: (50) the closest standard inductor is 27 h. the expected inductor ripple based on the chosen inductor is: (51) the inductor saturation current rating should be greater than the peak inductor current, i l(pk) . (52) 8.2.1.2.4 output capacitor selection the specified peak-to-peak led current ripple, i led(pp) , is: (53) the output capacitance required to achieve the target led current ripple is: (54) considering 40% derating factor under dc bias operation, four 4.7- f, 100-v rated x7r ceramic capacitors are used in parallel to achieve a combined output capacitance of 18.8 f. 8.2.1.2.5 input capacitor selection the input capacitor is required to reduce switching noise conducted through the input wires and reduced the input impedance of the led driver. the capacitor required to limit peak-to-peak input ripple voltage ripple, v in(pp) , to 70 mv is given by: (55) a 4.7- f, 50-v x7r ceramic capacitor is selected. 8.2.1.2.6 main n-channel mosfet selection the mosfet ratings should exceed the maximum output voltage and rms switch current given by: (56) (57) a 60-v or a 100-v n-channel mosfet with current rating exceeding 3 a is required for this design. 8.2.1.2.7 rectifying diode selection the diode should be selected based on the following voltage and current ratings: (58) (59) a 60-v or a 100-v schottky diode with low reverse leakage current is suitable for this design. the package must be able to handle the power dissipation resulting from continuous forward current, i d , of 0.5 a. 28 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 d(br) o(ov) v v 1.2 50 1.2 60 u u max q(rms) led max d 0.8177 i i 0.5 2.48 1 d 1 0.8177 u u ds o(ov) v v 1.2 50 1.2 60 u u l(pp) 6 in 3 3 sw in(pp) i 0.5436 c 2.49 10 8 f v 8 390 10 70 10 ' u u u ' u u u u 6 led max out 3 3 sw d led(pp) i d 0.5 0.8177 c 10.48 10 f r i 390 10 4 25 10 u u u u u ' u u u u 3 led(pp) led i 0.05 i 25 10 ' u u in(min) max led l(pk) 6 3 max sw v d i 0.5 7 0.8177 i 3.01 1 d 2 l f 1 0.8177 2 27 10 390 10 u u u u u u u u in(min) max l(pp) 6 3 sw v d 7 0.8177 i 0.5436 l f 27 10 390 10 u u ' u u u u in(min) max 6 3 l(pp) sw v d 7 0.8177 l 26.76 10 i f 0.5485 390 10 u u u ' u u u d l max led i i (1 d ) i 0.5 u led l(pp) max i 0.5 i rr 0.2 0.5485 1 d 1 0.8177 ' u u
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 8.2.1.2.8 programming led current led current is based on the current shunt resistor, r cs and the v (csp-csn) threshold set by the voltage on the iadj pin v iadj . by default, iadj is tied to vcc via an external resistor to enable the internal reference voltage of 2.42 v that then sets the v (csp-csn) threshold to 172 mv. the current shunt resistor value is calculated by: (60) two 0.68- resistors are connected in parallel to achieve r cs of 0.34 . 8.2.1.2.9 setting switch current limit and slope compensation the switch current sense resistor, r is , is calculated by solving the following equations and choosing the lowest value: (61) (62) a standard value of 0.1 is selected. 8.2.1.2.10 deriving compensator parameters the modulator transfer function for the boost converter is derived for nominal v in voltage and corresponding duty cycle, d, and is given by the following equation. (see table 1 for more information.) (63) the proportional-integral compensator components c comp and r comp are obtained by solving the following expressions: (64) (65) the closet standard capacitor of 33 nf and resistor of 2.15 k is selected. the high frequency pole location is set by a 100 pf c hf capacitor. 8.2.1.2.11 setting start-up duration the soft-start capacitor required to achieve start-up in 8 ms is given by: (66) the closet standard capacitor of 100 nf is selected. 8.2.1.2.12 setting overvoltage protection threshold the overvoltage protection threshold of 50 v and hysteresis of 5 v is set by the r ov1 and r ov2 resistor divider. (67) copyright ? 2015, texas instruments incorporated submit documentation feedback 29 product folder links: tps92691 tps92691-q1 ov(hys) 3 ov2 6 6 v 5 r 250 10 20 10 20 10 u u u 6 6 6 3 9 out out ss ss led c v 18.8 10 38.4 c 12.5 10 t 12.5 10 8 10 81.9 10 i 0.5 u u u u u u u ? ? ? ? 1 ? 1 3 comp 3 9 p comp 1 1 r 2.165 10 c 14 10 33 10 u z u u u u 3 3 9 cs 0 comp 3 z r g 0.34 3.466 c 8.75 10 8.75 10 27.27 10 378.12 10 u u u u u u u ? ? z u ? 1 ? 1 3 z led 0 comp 3 p s s 1 1 ? i 378.12 10 g 3.466 ? v s s 1 1 14 10 ? ? z u ? 1 ? 1 ? ? z u ? 1 ? 1 is(limit) sl max is l(pk) v v d 0.525 0.2 0.8177 r 0.12 i 3.01 u u 6 3 sl sw is o(max) 2 v l f 2 0.2 27 10 390 10 r 0.11 v 38.4 u u u u u u u u cs led 0.172 0.172 r 0.344 i 0.5
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com (68) the standard resistor values of 249 k and 6.34 k are chosen. 8.2.1.2.13 pwm dimming considerations a series dimming fet is required to meet pwm dimming specification from 100% to 4% duty cycle. a 60-v, 2-a n-channel fet is suitable for this application. as an alternative, a 60-v, 2-a p-channel fet could be used to achieve pwm dimming. an external level-shift circuit is required to translate the ddrv signal to the gate of the p-channel dimming fet. the drive strength of 5 ma and gate-source voltage of 15 v are set by the 1-k and 2-k level-translator resistors and a small-signal n- channel mosfet, whose gate is connected to ddrv. by default, the pwm pin is connected to vcc through a 100-k resistor to enable the part upon start-up. 8.2.1.3 application curves these curves are for the boost led driver. ch1: switch node voltage; ch3: switch sense current resistor voltage; ch4: led current; time: 1 s/div figure 34. normal operation figure 33. efficiency vs input voltage ch1: input voltage; ch2: soft-start (ss) voltage; ch1: output voltage; ch3: input current; ch2: soft-start (ss) voltage; ch4: led current; time: 2 ms/div ch4: led current; time: 200 ms/div figure 35. startup transient figure 36. overvoltage protection 30 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 v in (v) efficiency (%) 7 8 9 10 11 12 13 14 15 16 17 18 75 80 85 90 95 100 d021 3 3 ov1 ov2 o(ov) 1.24 1.24 r r 250 10 6.36 10 v 1.24 50 1.24 u u ? ? ? ? 1 ? 1
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 ch1: gate voltage; ch2: external clk signal; ch1: ddrv voltage; ch2: pwm input; ch3: switch sense current resistor voltage; ch3: switch sense current resistor voltage; ch4: led current; time: 1 s/div ch4: led current; time: 2 ms/div figure 37. clock synchronization figure 38. pwm dimming transient ch1: ddrv voltage; ch2: pwm input; ch1: input voltage; ch3: switch sense current resistor voltage; ch2: imon voltage; ch4: led current; time: 4 s/div ch4: led current; time: 2 ms/div figure 39. pwm dimming transient (zoomed) figure 40. step input voltage transient and imon behavior copyright ? 2015, texas instruments incorporated submit documentation feedback 31 product folder links: tps92691 tps92691-q1
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com 8.2.2 typical buck-boost led driver figure 41. buck-boost led driver 32 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 8.2.2.1 design requirements buck-boost led drivers provide the flexibility needed in applications that support multiple led load configurations. for such applications, it is necessary to modify the design procedure presented in application information to account for the wider range of output voltage and led current specifications. this design is based on the maximum output power p o(max) , set by the lumen output specified for the lighting application. the design procedure for a battery connected application with 3 to 9 leds in series and maximum 15 w output power is outlined in this section. for applications that have a fixed number of leds and a narrow led current range (for brightness correction), design equations provided in the application information and simplified design procedure, similar to one outlined in typical boost led driver for boost led driver, are recommended for developing an optimized circuit with lower bill of material (bom) cost. table 3. design parameters parameter test conditions min typ max unit input characteristics input voltage range 7 14 18 v input uvlo setting 4.5 v output characteristics led forward voltage 3.2 v number of leds in series 3 6 9 v o output voltage led+ to led ? 9.6 19.2 28.8 v i led output current 500 750 1500 ma i led(pp) led current ripple 5% r d led string resistance 1 2 3 p o(max) maximum output power 15 w pwm dimming range 240-hz pwm frequency 4% 100% systems characteristics p o(bdry) output power at ccm-dcm boundary 5 w condition v in(pp) input voltage ripple 70 mv v o(ov) output overvoltage protection threshold 40 v v ov(hys) output overvoltage protection hysteresis 5 v t ss soft-start period 8 ms switching frequency 390 khz 8.2.2.2 detailed design procedure 8.2.2.2.1 calculating duty cycle solving for d, d max , and d min : (69) (70) (71) 8.2.2.2.2 setting switching frequency solving for r t resistor: copyright ? 2015, texas instruments incorporated submit documentation feedback 33 product folder links: tps92691 tps92691-q1 o o in v 19.2 d 0.5783 v v 19.2 14 o(min) min o(min) in(max) v 9.6 d 0.3478 v v 9.6 18 o(max) max o(max) in(min) v 28.8 d 0.8045 v v 28.8 7
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com (72) 8.2.2.2.3 inductor selection the inductor is selected to meet the ccm-dcm boundary power requirement, p o(bdry) . typically, the boundary condition is set to enable ccm operation at the lowest possible operating power based on minimum led forward voltage drop and led current. in most applications, p o(bdry) is set to be 1/3 of the maximum output power, p o(max) . the inductor value is calculated for maximum input voltage, v in(max) , and output voltage, v o(max) : (73) the closest standard value of 33 h is selected. the inductor ripple current is given by: (74) the inductor saturation rating should exceed the calculated peak current which is based on the maximum output power using the following expression: (75) 8.2.2.2.4 output capacitor selection the output capacitor should be selected to achieve the 5% peak-to-peak led current ripple specification. based on the maximum power, the capacitor is calculated as follows: (76) a minimum of four 10- f, 50-v x7r ceramic capacitors in parallel are needed to meet the led current ripple specification over the entire range of output power. additional capacitance may be required based on the derating factor under dc bias operation. 8.2.2.2.5 input capacitor selection the input capacitor is calculated based on the peak-to-peak input ripple specifications, v in(pp) . the capacitor required to limit the ripple to 70 mv over range of operation is calculated using: (77) a parallel combination of four 10- f, 50-v x7r ceramic capacitors are used for a combined capacitance of 40 f. additional capacitance may be required based on the derating factor under dc bias operation. 8.2.2.2.6 main n-channel mosfet selection calculating the minimum transistor voltage and current rating: (78) 34 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 ds o(ov) in(max) v 1.2 v v 1.2 (40 18) 69.6 u u o(max) 6 in 3 sw in(pp) o(min) in(min) p 15 c 33.1 10 f v v v 390 10 0.07 9.6 7 u u ' u u u u 6 out 3 15 c 30.9 10 390 10 1 0.075 9.6 7 u u u u u o(max) out sw d(min) led(pp) o(min) in(min) p c f r i v v u u ' u l(pk) 6 3 1 1 9.6 7 i 15 3.863 9.6 7 2 33 10 390 10 9.6 7 u u ? u u u u u ? 1 o(min) in(min) l(pk) o(max) o(min) in(min) sw o(min) in(min) v v 1 1 i p v v 2 l f v v u u ? ? u u u ? 1 in(min) max l(pp) 6 3 sw v d 7 0.8045 i 0.4376 l f 33 10 390 10 u u ' u u u u 6 2 2 3 o(bdry) sw o(max) in(max) 1 1 l 31.46 10 1 1 1 1 2 5 390 10 2 p f 28.8 18 v v u u u u u u u u ? ? ? ? 1 ? 1 10 10 3 t 1.047 1.047 3 sw 1.432 10 1.432 10 r 20.05 10 f 390 10 u u u u
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 (79) this application requires a 60-v or 100-v n-channel mosfet with a current rating exceeding 3 a. 8.2.2.2.7 rectifier diode selection calculating the minimum schottky diode voltage and current rating: (80) (81) this application requires a 60-v or 100-v schottky diode with a current rating exceeding 1.5 a. ti recommends a single high-current diode instead of paralleling multiple lower-current-rated diodes to ensure reliable operation over temperature. 8.2.2.2.8 setting switch current limit and slope compensation solving for r is : (82) (83) a standard resistor of 0.1 is selected based on the lower of the two calculated values. the resistor ensures stable current loop operation with no subharmonic oscillations over the entire input and output voltage ranges. 8.2.2.2.9 programming led current the led current can be programmed to match the led string configuration by using a resistor divider, r adj1 and r adj2 , from v cc to gnd for a given sense resistor, r cs , as shown in figure 21 . to maximize the accuracy, the iadj pin voltage is set to 2.1 v for the specified led current of 1.5 a. the current sense resistor, r cs , is then calculated as: (84) a standard resistor of 0.1 is selected. table 4 summarizes the iadj pin voltage and the choice of the r adj1 and r adj2 resistors for different current settings. table 4. design requirements led current iadj voltage (v iadj ) r adj1 r adj2 500 ma 700 mv 10.2 k 100 k 750 ma 1.05 v 16.2 k 100 k 1.5 a 2.1 v 39.2 k 100 k 8.2.2.2.10 deriving compensator parameters a simple integral compensator provides a good starting point to achieve stable operation across the wide operating range. the modulator transfer function with the lowest frequency pole location is calculated based on maximum output voltage, v o(max) , duty cycle, d max , led dynamic resistance, r d(max) , and minimum led string current, i led(min) . (see table 1 for more information.) (85) copyright ? 2015, texas instruments incorporated submit documentation feedback 35 product folder links: tps92691 tps92691-q1 3 z led 0 comp 3 p s s 1 1 ? i 82.92 10 g 1.876 ? v s s 1 1 8.68 10 ? ? z u ? 1 ? 1 ? ? z u ? 1 ? 1 iadj cs led(max) v 2.1 r 0.1 14 i 14 1.5 u u is(limit) sl max is l(pk) v v d 0.525 0.2 0.8045 r 0.094 i 3.863 u u 6 3 sl sw is o(max) 2 v l f 2 0.2 33 10 390 10 r 0.179 v 28.8 u u u u u u u u d led(max) i i 1.5 d(br) o(ov) in(max) v 1.2 v v 1.2 (40 18) 69.6 u u o(max) in(min) q(rms) in(min) o(min) p v 15 7 i 1 1 2.82 v v 7 9.6 ? ? ? ? 1 ? 1
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com the compensation capacitor needed to achieve stable response is: (86) a 100 nf capacitor is selected. a proportional integral compensator can be used to achieve higher bandwidth and improved transient performance. however, it is necessary to experimentally tune the compensator parameters over the entire operating range to ensure stable operation. 8.2.2.2.11 setting startup duration solving for soft-start capacitor, c ss , based on 8-ms startup duration: (87) a 100-nf soft-start capacitor is selected. 8.2.2.2.12 setting overvoltage protection threshold solving for resistors, r ov1 and r ov2 : (88) (89) the closest standard values of 249 k and 7.87 k along with a 60-v pnp transistor are used to set the ovp threshold to 40 v with 5 v of hysteresis. 8.2.2.2.13 pwm dimming consideration a 60-v, 2-a p-channel fet is used in conjunction with an external level-shift circuit to achieve pwm dimming. the drive strength of 5 ma and gate-source voltage of 15 v are set by the 1-k and 2-k level-translator resistors and a small-signal n-channel mosfet, whose gate is connected to ddrv. 8.2.2.3 application curves these curves are for the buck-boost led driver. v in = 14 v figure 42. line regulation (3 leds at 1.5 a and 9 leds at figure 43. led current vs iadj voltage 500 ma) 36 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 6 out out(max) 6 6 3 9 ss ss led(min) c v 40 10 28.8 c 12.5 10 t 12.5 10 8 10 71.2 10 i 0.5 u u u u u u u ? ? ? ? ? 1 ? 1 3 3 9 cs comp 3 p 8.75 10 r 8.75 10 0.1 c 100.8 10 8.68 10 u u u u u z u v in (v) led current (ma) led current (ma) 8 9 10 11 12 13 14 15 16 17 18 1496 492 1497 494 1498 496 1499 498 1500 500 1501 502 1502 504 1503 506 1504 508 d022 leds = 3 leds = 9 v iadj (v) led current (ma) 0 0.28 0.56 0.84 1.12 1.4 1.68 1.96 2.24 0 200 400 600 800 1000 1200 1400 1600 d023 leds = 3 3 3 ov2 ov1 o(ov) 1.24 r 1.24 250 10 r 7.89 10 v 0.7 40 0.7 u u u u ov(hys) 3 ov2 6 6 v 5 r 250 10 20 10 20 10 u u u
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 v in = 14 v figure 44. efficiency from 100 ma to 1.5 a 9 power supply recommendations this device is designed to operate from an input voltage supply range between 4.5 v and 65 v. the input could be a car battery or another preregulated power supply. if the input supply is located more than a few inches from the tps92691/-q1 device, additional bulk capacitance or an input filter may be required in addition to the ceramic bypass capacitors to address noise and emi concerns. 10 layout 10.1 layout guidelines ? the performance of the switching regulator depends as much on the layout of the pcb as the component selection. following a few simple guidelines will maximize noise rejection and minimize the generation of emi within the circuit. ? discontinuous currents are the most likely to generate emi. therefore, take care when routing these paths. the main path for discontinuous current in the tps92691/-q1 buck regulator contains the input capacitor, c in , the recirculating diode, d, the n-channel mosfet, q1, and the sense resistor, r is . in the tps92691/-q1 boost regulator, the discontinuous current flows through the output capacitor c out , diode, d, n-channel mosfet, q1, and the current sense resistor, r is . in buck-boost regulator, both loops are discontinuous and should be carefully laid out. these loops should be kept as small as possible and the connection between all the components should be short and thick to minimize parasitic inductance. in particular, the switch node (where l, d, and q1 connect) should be just large enough to connect the components. to minimize excessive heating, large copper pours can be placed adjacent to the short current path of the switch node. ? csp and csn traces should be routed together with kelvin connections to the current sense resistor as short as possible. if needed, use common mode and differential mode noise filters to attenuate switching and diode reverse recovery noise from affecting the internal current sense amplifier. ? the comp, is, ovp, pwm, and iadj pins are all high-impedance inputs that couple external noise easily; therefore, the loops containing these nodes should be minimized whenever possible. ? in some applications, the led or led array can be far away from the tps92691/-q1, or on a separate pcb connected by a wiring harness. when an output capacitor is used and the led array is large or separated from the rest of the regulator, the output capacitor should be placed close to the leds to reduce the effects of parasitic inductance on the ac impedance of the capacitor. ? the tps92691/-q1 has an exposed thermal pad to aid power dissipation. adding several vias under the exposed pad helps conduct heat away from the device. the junction-to-ambient thermal resistance varies with application. the most significant variables are the area of copper in the pcb and the number of vias under the exposed pad. the integrity of the solder connection from the device exposed pad to the pcb is critical. excessive voids greatly decrease the thermal dissipation capacity. copyright ? 2015, texas instruments incorporated submit documentation feedback 37 product folder links: tps92691 tps92691-q1 i led (ma) effiency (%) 100 200 300 400 500 700 1000 2000 40 50 60 70 80 90 100100 d024 leds = 3 leds = 5 leds = 7 leds = 9
tps92691 , tps92691-q1 slvsd68 ? december 2015 www.ti.com 10.2 layout example figure 45. layout recommendation 38 submit documentation feedback copyright ? 2015, texas instruments incorporated product folder links: tps92691 tps92691-q1 tps92691q vin rt/sy pwm ss iadj imon comp agnd input conn vcc is pgnd gate ddrv csp ovp csn vin led+ led+ gnd buck-boost boost via to bottom ground plane
tps92691 , tps92691-q1 www.ti.com slvsd68 ? december 2015 11 device and documentation support 11.1 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 5. related links technical tools & support & parts product folder sample & buy documents software community tps92691 click here click here click here click here click here tps92691-q1 click here click here click here click here click here 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks powerpad, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2015, texas instruments incorporated submit documentation feedback 39 product folder links: tps92691 tps92691-q1
package option addendum www.ti.com 17-dec-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps92691pwp active htssop pwp 16 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 92691 tps92691pwpr active htssop pwp 16 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 92691 TPS92691QPWPQ1 active htssop pwp 16 90 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 92691q tps92691qpwprq1 active htssop pwp 16 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 92691q tps92691qpwptq1 active htssop pwp 16 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 125 92691q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 17-dec-2015 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tps92691, tps92691-q1 : ? catalog: tps92691 ? automotive: tps92691-q1 note: qualified version definitions: ? catalog - ti's standard catalog product ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps92691pwpr htssop pwp 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 tps92691qpwprq1 htssop pwp 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 tps92691qpwptq1 htssop pwp 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 13-feb-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps92691pwpr htssop pwp 16 2000 367.0 367.0 38.0 tps92691qpwprq1 htssop pwp 16 2000 367.0 367.0 38.0 tps92691qpwptq1 htssop pwp 16 250 210.0 185.0 35.0 package materials information www.ti.com 13-feb-2016 pack materials-page 2

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